Group iii nitride semiconductor device, production method therefor, and power converter

ABSTRACT

A method for producing a semiconductor device, includes forming a first carrier transport layer including a Group III nitride semiconductor, forming a mask on a region of the first carrier transport layer, selectively re-growing a second carrier transport layer on an unmasked region of the first carrier transport layer, the second carrier transport layer including a Group III nitride semiconductor, and selectively growing a carrier supply layer on the second carrier transport layer, the carrier supply layer including a Group III nitride semiconductor having a bandgap different from that of the Group III nitride semiconductor of the second carrier transport layer.

The present application is a Divisional Application of U.S. patentapplication Ser. No. 12/923,405, filed on Sep. 20, 2010, which is basedon and claims priority from Japanese Patent Application No. 2009-219254,filed on Sep. 24, 2009, the entire contents of which is incorporatedherein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a Group III nitride semiconductordevice, and to a method for producing the device. More particularly, thepresent invention relates to a semiconductor device with reducedon-state resistance (e.g., an HEMT (high electron mobility transistor),also called an HFET (heterostructure field effect transistor), the termof HEMT is used in the present specification, or a diode), and to amethod for producing the device. The present invention also relates to apower converter including such a Group III nitride semiconductor device.

2. Background Art

Group III nitride semiconductors have been widely used as a material forlight-emitting devices. Also, Group III nitride semiconductors areenvisaged as a material for power devices, since they exhibit highelectron mobility and have a breakdown field strength about 10 timesthat of Si. Hitherto developed power devices include an HEMT (highelectron mobility transistor) in which a two-dimensional electron gas(2DEG) layer formed at a heterojunction interface serves a channel. Whena GaN HEMT is produced so as to have the same structure as aconventional HEMT (e.g., GaAs HEMT), the GaN HEMT exhibits a normally-oncharacteristic; i.e., the HEMT is in an ON state under application of novoltage to a gate electrode. However, an HEMT exhibiting a normally-oncharacteristic poses a safety problem. Therefore, there have beenproposed various HEMT structures which realize a normally-offcharacteristic (i.e., no current flows between a source electrode and adrain electrode under application of no voltage to a gate electrode).

For example, Japanese Patent Application Laid-Open (kokai) No.2008-147593 discloses an HEMT which realizes a normally-offcharacteristic; specifically, an HEMT having an MIS structure in which acarrier supply layer is not formed directly below a gate electrode. Thisstructure realizes a normally-off characteristic, since a 2DEG layer isnot formed in a region directly below the gate electrode. In order toachieve this structure, Japanese Patent Application Laid-Open (kokai)No. 2008-147593 discloses a method for exposing a surface of a carriertransport layer by removing a portion of a carrier supply layer throughdry etching.

Japanese Patent Application Laid-Open (kokai) No. 2009-99691 discloses amethod for producing an HEMT, in which a first carrier supply layer isformed on a carrier transport layer; a mask is formed on a specificregion of the first carrier supply layer; two second carrier supplylayers are formed, through selective re-growth, on unmasked regions ofthe first carrier supply layer so that the second carrier supply layersare separated from each other; a source electrode is formed on one ofthe second carrier supply layers; a drain electrode is formed on theother second carrier supply layer; and a gate electrode is formed on themask.

However, when the structure disclosed in Japanese Patent ApplicationLaid-Open (kokai) No. 2008-147593 is produced through the method usingselective re-growth disclosed in Japanese Patent Application Laid-Open(kokai) No. 2009-99691, problems arise in that, for example, impurities,etc. are incorporated at the interface between a carrier transport layerand a carrier supply layer when the carrier supply layer is grown on thecarrier transport layer, and flatness of the interface between theselayers is degraded, which results in reduction in mobility of 2DEGgenerated at the heterojunction interface between the carrier transportlayer and the carrier supply layer, and an increase in on-stateresistance.

SUMMARY OF THE INVENTION

In view of the foregoing, an object of the present invention is toprovide a Group III nitride semiconductor device with reduced on-stateresistance. Another object of the present invention is to provide amethod for producing the semiconductor device. Yet another object of thepresent invention is to provide a power converter comprising thesemiconductor device.

In a first aspect of the present invention, there is provided asemiconductor device comprising:

a first carrier transport layer formed of a Group III nitridesemiconductor;

a second carrier transport layer which is formed through selectivere-growth of a Group III nitride semiconductor and is provided on aregion of the first carrier transport layer; and

a carrier supply layer formed through selective growth of a Group IIInitride semiconductor having a bandgap energy (hereinafter may bereferred to simply as “bandgap”) larger than that of the Group IIInitride semiconductor of the second carrier transport layer, the carriersupply layer being provided on the second carrier transport layer.

As used herein, “Group III nitride semiconductor” encompasses asemiconductor represented by the formula Al_(x)Ga_(y)In_(z)N (x+y+z=1,0≦x, y, z≦1); such a semiconductor in which a portion of Al, Ga, or Inis substituted by another Group 13 element (Group 3B element) (i.e., Bor Tl), or a portion of N is substituted by another Group 15 element(Group 5B element) (i.e., P, As, Sb, or Bi). Specific examples of theGroup III nitride semiconductor include those containing at least Ga,such as GaN, InGaN, AlGaN, and AlGaInN. Generally, Si is employed as ann-type impurity, and Mg is employed as a p-type impurity.

Each of the first carrier transport layer, the second carrier transportlayer, and the carrier supply layer may be formed of a single layer or aplurality of layers. Generally, the first carrier transport layer andthe second carrier transport layer are formed of the same Group IIInitride semiconductor (e.g., GaN). However, these layers are notnecessarily formed of the same Group III nitride semiconductor.

Preferably, the second carrier transport layer is formed of undoped GaNfor the purpose of preventing reduction in mobility of 2DEG. When thesecond carrier transport layer is formed of a plurality of layers,preferably, at least a layer (among the layers) which is in contact withthe carrier supply layer is formed of undoped GaN.

The carrier supply layer may be formed of any Group III nitridesemiconductor having a bandgap larger than that of the Group III nitridesemiconductor of the second carrier transport layer. The carrier supplylayer may be an undoped layer, or may be doped with an n-type impurity.The carrier supply layer may have a cap layer thereon.

A single layer or a plurality of layers formed of a Group III nitridesemiconductor may be further provided on the second carrier transportlayer. For example, there may be provided, on the carrier supply layer,one or more layer pairs, each pair including an under layer formedthrough selective growth of a Group III nitride semiconductor, and anupper layer formed through selective growth of a Group III nitridesemiconductor having a bandgap larger than that of the Group III nitridesemiconductor of the under layer and wherein an under layer whichcontacts with the carrier supply layer has a bandgap larger than that ofthe Group III nitride semiconductor of the carrier supply layer. When aplurality of layer pairs are provided on the carrier supply layer, thesmaller-bandgap layers of the layer pairs may be formed of differentGroup III nitride semiconductors, and the larger-bandgap layers of thelayer pairs may be formed of different Group III nitride semiconductors.

The present invention is applicable to a semiconductor device in which a2DEG layer is formed in the vicinity of the heterojunction interfacebetween the second carrier transport layer and the carrier supply layerand on the side of the second carrier transport layer, and the 2DEGlayer serves as a channel. For example, the present invention isapplicable to an HEMT, an HBT (heterojunction bipolar transistor), and adiode.

A second aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to the first aspect,wherein laminate structures comprising a second carrier transport layerand a carrier supply layer are formed on two separate regions of asurface of the first carrier transport layer, and wherein thesemiconductor device further comprises a first electrode which isprovided on the carrier supply layer of one of the two separate regionsand which is electrically connected to the second carrier transportlayer of the same region; a second electrode which is provided on thecarrier supply layer of the other region and which is electricallyconnected to the second carrier transport layer of the same region; aninsulating film which is provided on a region of the first carriertransport layer sandwiched between the two separate regions and also onthe mutually facing lateral end surfaces of the two separate laminatestructures; and a control electrode formed on the insulating film.

The first electrode or the second electrode may be provided directly onthe corresponding carrier supply layer, or may be provided, via a GroupIII nitride semiconductor layer (e.g., a cap layer), on the carriersupply layer.

A third aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to the second aspect,wherein the insulating film is provided also on the top surfaces of thecarrier supply layers, and the control electrode extends, via theinsulating film, onto the carrier supply layers.

A fourth aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to the second or thirdaspect, wherein a portion or the entirety of the insulating film isformed of a plurality of layers.

A fifth aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to any of the second tofourth aspects, wherein a portion of the insulating film provided on thefirst carrier transport layer exhibits a property different from that ofa portion of the insulating film provided on the carrier supply layer.

As used herein, “different property” refers to the case where portionsof the insulating film exhibit different physical properties; forexample, the case where the portions are formed of different materials,the portions are formed of similar materials with differentcompositions, or the portions exhibit different crystallinities orcrystal structures.

A sixth aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to any of the second tofifth aspects, wherein the insulating film has a thickness smaller thanthat of the second carrier transport layer.

A seventh aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to any of the second tosixth aspects, wherein each of the first electrode and the secondelectrode is in ohmic contact with the corresponding second carriertransport layer.

An eighth aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to any of the second toseventh aspects, wherein one of the first electrode and the secondelectrode is electrically connected to the control electrode.

A ninth aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to any of the first toeighth aspects, wherein the semiconductor device further comprises alayer for preventing transport of carriers in a region away from thesecond carrier transport layer (hereinafter the layer may be referred toas a “carrier transport preventing layer”), and the first carriertransport layer is provided on the carrier transport preventing layer.

A tenth aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to the ninth aspect,wherein the carrier transport preventing layer is formed of a Group IIInitride semiconductor having a conduction type different from that ofthe Group III nitride semiconductor of the first carrier transportlayer.

An eleventh aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to the ninth or tenthaspect, wherein the carrier transport preventing layer is formed of aGroup III nitride semiconductor having a bandgap larger than that of theGroup III nitride semiconductor of the first carrier transport layer.

A twelfth aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to the ninth or tenthaspect, wherein the carrier transport preventing layer is provided on alayer formed of a Group III nitride semiconductor having a bandgaplarger than that of the Group III nitride semiconductor of the carriertransport preventing layer.

A thirteenth aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to any of the first totwelfth aspects, wherein the carrier supply layer is formed of aplurality of layers.

A fourteenth aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to any of the first tothirteenth aspects, wherein the semiconductor device further comprises,on the carrier supply layer, one or more layer pairs, each pairincluding an under layer formed through selective growth of a Group IIInitride semiconductor, and an upper layer formed through selectivegrowth of a Group III nitride semiconductor having a bandgap larger thanthat of the Group III nitride semiconductor of the under layer andwherein an under layer which contacts with the carrier supply layer hasa bandgap larger than that of the Group III nitride semiconductor of thecarrier supply layer.

A fifteenth aspect of the present invention is drawn to a specificembodiment of the semiconductor device according to any of the first tofourteenth aspects, wherein lateral end surfaces of the second carriertransport layer and the carrier supply layer are inclined such that thearea of a horizontal cross section of the second carrier transport layerand the carrier supply layer parallel to the main surface of the deviceis reduced with increasing distance between the cross section and thefirst carrier transport layer.

In a sixteenth aspect of the present invention, there is provided apower converter comprising at least one of the semiconductor devices asrecited in the first to fifteenth aspects.

In a seventeenth aspect of the present invention, there is provided amethod for producing a semiconductor device, comprising:

forming a first carrier transport layer from a Group III nitridesemiconductor;

forming a mask on a region of the first carrier transport layer;

selectively re-growing a second carrier transport layer on an unmaskedregion of the first carrier transport layer from a Group III nitridesemiconductor; and

selectively growing a carrier supply layer on the second carriertransport layer from a Group III nitride semiconductor having a bandgapdifferent from that of the Group III nitride semiconductor of the secondcarrier transport layer.

An eighteenth aspect of the present invention is drawn to a specificembodiment of the method for producing the semiconductor deviceaccording to seventeenth aspect, wherein laminate structures comprisingthe second carrier transport layer and the carrier supply layer areformed on two separate regions of a surface of the first carriertransport layer, the two separate regions being separated by the mask;and

wherein the method further comprises;

removing the mask;

forming an insulating film which is provided on a region of the firstcarrier transport layer sandwiched between the two separate regions andalso on the mutually facing lateral end surfaces of the two separatelaminate structures; and

forming a control electrode formed on the insulating film.

A nineteenth aspect of the present invention is drawn to a specificembodiment of the method for producing the semiconductor deviceaccording to eighteenth aspect, comprising:

forming the insulating film also on the top surfaces of the carriersupply layers, and

forming the control electrode extends, via the insulating film, onto thecarrier supply layers.

A twentieth aspect of the present invention is drawn to a specificembodiment of the method for producing the semiconductor deviceaccording to eighteenth aspect, further comprising:

forming a first electrode on the carrier supply layer of one of the twoseparate regions to be electrically connected to the second carriertransport layer of the same region;

forming a second electrode on the carrier supply layer of the otherregion to be electrically connected to the second carrier transportlayer of the same region.

In the semiconductor device according to the first aspect, a 2DEG layeris formed in the vicinity of the heterojunction interface between thesecond carrier transport layer and the carrier supply layer and on theside of the second carrier transport layer, and the 2DEG layer serves asa channel. Since the second carrier transport layer is selectivelyre-grown on the first carrier transport layer, selectivere-growth-associated impurities are incorporated at the heterojunctioninterface between the first carrier transport layer and the secondcarrier transport layer. However, the amount of impurities contained ina portion of the second carrier transport layer is reduced withincreasing distance between the portion and the first carrier transportlayer. Therefore, virtually no selective re-growth-associated impuritiesare observed at the heterojunction interface between the second carriertransport layer and the carrier supply layer. Since the carrier supplylayer is continuously grown on the second carrier transport layer afterselective re-growth of the second carrier transport layer, flatness ofthe heterojunction interface between the second carrier transport layerand the carrier supply layer is higher than that of the heterojunctioninterface between the first carrier transport layer and the carriersupply layer in the case where the carrier supply layer is selectivelyre-grown directly on the first carrier transport layer. Therefore,according to the semiconductor device of the present invention, therecan be prevented degradation of flatness associated with selectivere-growth, as well as reduction in mobility of 2DEG due to incorporatedimpurities associated with selective re-growth, and on-state resistancecan be reduced.

As described in the second aspect, the present invention is applicableto a semiconductor device in which conduction between first and secondelectrodes is controlled by means of a control electrode (e.g., anHEMT), and realizes a semiconductor device exhibiting low on-stateresistance.

As described in the third aspect, when the control electrode is alsoformed, via the insulating film, on the carrier supply layer, a largeramount of electrons can be accumulated at the interface between theinsulating film and lateral end surfaces of the second carrier transportlayer and the carrier supply layer, and the concentration of 2DEGgenerated below the control electrode can be further increased,resulting in further reduction in on-state resistance.

As described in the fourth aspect, a portion or the entirety of theinsulating film may be formed of a plurality of layers. As described inthe fifth aspect, a portion of the insulating film provided on the firstcarrier transport layer may exhibit a property different from that of aportion of the insulating film provided on the carrier supply layer.

According to the sixth aspect, a larger amount of electrons can beaccumulated at the interface between the insulating film and lateral endsurfaces of the second carrier transport layer and the carrier supplylayer, and on-state resistance can be further reduced.

According to the seventh aspect, the on-state resistance of thesemiconductor device of the second aspect can be further reduced.

As described in the eighth aspect, the present invention is applicableto a diode having a configuration in which a short circuit is formedbetween the control electrode and either of the first and secondelectrodes of the semiconductor device of the second aspect, andrealizes a diode exhibiting low on-state voltage and high breakdownvoltage.

As described in the ninth to twelfth aspects, when the carrier transportpreventing layer is provided, flow of electrons can be prevented in aregion away from the heterojunction interface between the second carriertransport layer and the carrier supply layer, and off-state leakagecurrent can be reduced.

As described in the thirteenth aspect, the carrier supply layer may beformed of a plurality of layers.

According to the fourteenth aspect, a plurality of 2DEG layers can beformed, which realizes a semiconductor device exhibiting lower on-stateresistance.

According to the fifteenth aspect, electric field crowding is relaxed,and thus breakdown voltage can be improved.

As described in the sixteenth aspect, when the semiconductor device ofthe present invention is applied to a power converter, the powerconverter can attain low loss and high performance.

According to the seventeenth aspect, the amount of impuritiesincorporated upon selective re-growth of the second carrier transportlayer on the first carrier transport layer is reduced as growth of thesecond carrier transport layer proceeds. Therefore, virtually noimpurities are incorporated at the heterojunction interface between thesecond carrier transport layer and the carrier supply layer. Inaddition, formation of the second carrier transport layer improvesflatness of the heterojunction interface between the second carriertransport layer and the carrier supply layer. Thus, a semiconductordevice exhibiting low on-state resistance can be produced.

BRIEF DESCRIPTION OF THE DRAWINGS

Various other objects, features, and many of the attendant advantages ofthe present invention will be readily appreciated as the same becomesbetter understood with reference to the following detailed descriptionof the preferred embodiments when considered in connection with theaccompanying drawings, in which:

FIG. 1 shows the configuration of an HEMT 100 according to Embodiment 1;

FIGS. 2A to 2D are sketches showing processes for producing the HEMT 100according to Embodiment 1;

FIG. 3 shows the configuration of an HEMT 200 according to Embodiment 2;

FIG. 4 shows the configuration of an HEMT 300 according to Embodiment 3;

FIG. 5 shows the configuration of an HEMT 400 according to Embodiment 4;

FIG. 6 shows the configuration of an HEMT 500 according to Embodiment 5;

FIG. 7 shows the configuration of an HEMT 600 according to Embodiment 6;

FIG. 8 shows the configuration of an HEMT 700 according to Embodiment 7;

FIG. 9 shows the configuration of a diode 800 according to Embodiment 8;and

FIG. 10 shows the configuration of a power factor improving circuit 900according to Embodiment 9.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Specific embodiments of the present invention will next be describedwith reference to the drawings. However, the present invention is notlimited to the embodiments.

Embodiment 1

FIG. 1 shows the configuration of an HEMT 100 according to Embodiment 1.

The HEMT 100 includes an Si substrate 101; an AlN buffer layer 102provided on the substrate 101; and a first carrier transport layer 103formed of undoped GaN and provided on the AlN buffer layer 102.

Two separate second carrier transport layers 104 formed of undoped GaNare provided on two separate regions of the first carrier transportlayer 103. Carrier supply layers 105 formed of Al_(0.25)Ga_(0.75)N arerespectively provided on the two separate second carrier transportlayers 104. The second carrier transport layer 104 and the carriersupply layer 105 form a heterojunction therebetween. The heterojunctionforms a channel on which electrons conduct. The second carrier transportlayer 104 and the carrier supply layer 105 are respectively formedthrough selective crystal re-growth.

A source electrode 106 is formed on one of the two separate carriersupply layers 105, and a drain electrode 107 is formed on the othercarrier supply layer 105. Each of the source electrode 106 and the drainelectrode 107 is formed of Ti/Al (Ti and Al are sequentially provided onthe carrier supply layer).

An SiO₂ insulating film 108 is provided on a region of the first carriertransport layer 103 which is located between two separate laminatestructures each including the second carrier transport layer 104 and thecarrier supply layer 105, and on which the second carrier transportlayers 104 are not provided. The insulating film 108 is also provided ontwo mutually facing lateral end surfaces 111 of the two laminatestructures each including the second carrier transport layer 104 and thecarrier supply layer 105, and is also provided on the carrier supplylayers 105.

A gate electrode 109 is provided, via the insulating film 108, on aregion of the first carrier transport layer 103 on which the secondcarrier transport layers 104 are not provided and on the two lateral endsurfaces 111. The gate electrode 109 is formed of Ni/Au (Ni and Au aresequentially provided on the insulating film 108). The gate electrode109 is also provided, via the insulating film 108, on the carrier supplylayers 105 in the vicinity of the lateral end surfaces 111 such that thegate electrode 109 extends 0.5 μm from the lateral end surfaces 111toward the source electrode 106 and the drain electrode 107,respectively. When the gate electrode 109 is provided so as to extend inthis manner, in the case where positive voltage is applied to the gateelectrode 109, a larger amount of electrons can be accumulated in thechannel in the vicinity of the lateral end surfaces 111, and theconcentration of 2DEG can be further increased in a region of thechannel located below the thus-extended gate electrode 109. Therefore,on-state resistance can be further reduced.

The first carrier transport layer 103 has a thickness of 2 μm; thesecond carrier transport layer 104 has a thickness of 100 nm; thecarrier supply layer 105 has a thickness of 25 nm; and the insulatingfilm 108 has a thickness of 40 nm. The distance between the sourceelectrode 106 and the gate electrode 109 is 1.5 μm, and the distancebetween the gate electrode 109 and the drain electrode 107 is 6.5 μm;i.e., the HEMT 100 has an asymmetric configuration in which the gateelectrode 109 is provided proximal to the source electrode 106. Thus,the gate electrode 109 is located nearer to the source electrode 106than to the drain electrode 107 for the purpose of improving breakdownvoltage.

The substrate 101 may be formed of, in place of Si, any known materialwhich has been conventionally used in a growth substrate for a Group IIInitride semiconductor (e.g., sapphire, SiC, ZnO, spinel, or GaN).

The buffer layer 102 may be formed of GaN in place of AlN, or may beformed of a plurality of layers (e.g., AlN/GaN). The first carriertransport layer 103 may be formed of any Group III nitridesemiconductor, but is preferably formed of GaN, from the viewpoint of,for example, crystallinity. The first carrier transport layer 103 may bedoped with an n-type impurity, or may be formed of a plurality oflayers. The first carrier transport layer 103 may be formed directly onthe substrate 101 without formation of the buffer layer 102.

The second carrier transport layer 104 is formed of GaN, and the carriersupply layer 105 is formed of AlGaN. However, each of the second carriertransport layer 104 and the carrier supply layer 105 may be formed ofany Group III nitride semiconductor, so long as the bandgap of the GroupIII nitride semiconductor of the carrier supply layer 105 is larger thanthat of the Group III nitride semiconductor of the second carriertransport layer 104. For example, the second carrier transport layer 104may be formed of InGaN, and the carrier supply layer 105 may be formedof GaN or AlGaN. The carrier supply layer 105 may be doped with animpurity such as Si (i.e., n-type). The carrier supply layer 105 mayhave a cap layer thereon. The second carrier transport layer 104 and thefirst carrier transport layer 103 may be formed of the same Group IIInitride semiconductor material or different Group III nitridesemiconductor materials.

By virtue of the heterojunction formed between the second carriertransport layer 104 and the carrier supply layer 105, a 2DEG layer,i.e., a channel, (a portion shown by a dotted line in FIG. 1) is formedin the vicinity of the heterojunction interface 110 between the secondcarrier transport layer 104 and the carrier supply layer 105 and on theside of the second carrier transport layer 104. The second carriertransport layers 104 and the carrier supply layers 105 are formed ofportions 104 a and 105 a and portions 104 b and 105 b, which areseparated by the gate electrode 109. Therefore, the 2DEG layer i.e., thechannel, is formed in separate two regions; i.e., a region in which thesource electrode 106 is formed on the carrier supply layer 105(source-gate region) and a region in which the drain electrode 107 isformed on the carrier supply layer 105 (gate-drain region).

Each of the source electrode 106 and the drain electrode 107 is in ohmiccontact with the second carrier transport layer 104 via the carriersupply layer 105 by means of the tunnel effect. Each of the sourceelectrode 106 and the drain electrode 107 may be formed of, for example,Ti/Au in place of Ti/Al. Each electrode may be formed of a material forproviding Schottky contact, but such a material is not preferred fromthe viewpoint of reduction in on-state resistance. For the purpose ofattaining good ohmic contact, a region of the carrier supply layer 105or the second carrier transport layer 104 directly below the sourceelectrode 106 or the drain electrode 107 may be doped with Si at highconcentration, or the thickness of the carrier supply layer 105 directlybelow the source electrode 106 or the drain electrode 107 may bereduced.

The insulating film 108 serves as both a gate insulating film and aprotective film. The insulating film 108 may be formed of, in place ofSiO₂, SiN_(x), Al₂O₃, HfO₂, ZrO₂, AlN, or a similar material. Althoughthe insulating film 108 is formed of a single layer, a portion or theentirety of the insulating film 108 may be formed of a plurality oflayers. For example, when the insulating film 108 includes two layers,the film may be formed of, for example, SiO₂/ZrO₂ (which refers to thecase where SiO₂ and ZrO₂ are sequentially provided on the first carriertransport layer 103, the same shall apply hereinafter in thisparagraph), SiO₂/Al₂O₃, SiO₂/HfO₂, SiN/SiO₂, or Al₂O₃/ZrO₂.

When the insulating film 108 includes three layers, the film may beformed of, for example, SiN/SiO₂/ZrO₂ or SiO₂/Al₂O₃/HfO₂.

The gate electrode 109 may be formed of, for example, Ti/Al, W, orpolysilicone in place of Ni/Au.

In the HEMT 100, when bias voltage is not applied to the gate electrode109, the 2DEG layers separated in the source-gate region and thegate-drain region are not electrically connected. Therefore, currentdoes not flow between the source electrode and the drain electrode(i.e., OFF state). Thus, the HEMT 100 exhibits a normally-offcharacteristic. Meanwhile, when a bias voltage equal to or higher thanthe threshold voltage is applied to the gate electrode 109, electronsare accumulated in a region which is in contact with the gate electrode109 via the insulating film 108; specifically, in the vicinity of thesurface of the first carrier transport layer 103 on which the secondcarrier transport layers 104 are not provided (i.e., a region in whichthe insulating film 108 is in contact with the first carrier transportlayer 103), and in the vicinity of the mutually facing lateral endsurfaces 111 of the second carrier transport layers 104 and the carriersupply layers 105. By means of the thus-accumulated electrons, the 2DEGlayer located in the source-gate region is electrically connected to the2DEG layer located in the gate-drain region. As a result, current flowsbetween the source electrode and the drain electrode (i.e., ON state).

In the HEMT 100, since the second carrier transport layer 104 isselectively re-grown on the first carrier transport layer 103 by using amask 113 (FIG. 2B), impurities are incorporated at the interface betweenthe first carrier transport layer 103 and the second carrier transportlayer 104.

That is, a substrate on which the layers from the buffer layer 102 tothe first carrier transport layer 103 are grown is taken out of i.e., aMOCVD growth chamber and the mask 113 for selective re-growth isdeposited on the first carrier transport layer 103 in e.g., a plasmaprocess chamber. After the substrate with the mask 113 is returned intothe MOCVD growth chamber, the second carrier transport layer 104 isselectively re-grown on the area of the first carrier transport layer103, the area on which the mask 113 is not formed. The surface of thefirst carrier transport layer 103 is contaminated with impurities at thestages of the plasma process for depositing the mask 113 and transportprocesses of the substrate between the MOCVD growth chamber and theplasma process chamber. Hereinafter the impurities contaminating thesurface of the first carrier transport layer 103 in the processes beforethe re-growth are called as re-growth-associated impurities.

However, even if the surface of the first carrier transport layer 103 iscontaminated with impurities in the process before the re-growth, theamount of re-growth-associated impurities contained in the secondcarrier transport layer 104 is reduced in accordance with increasingdistance from the interface between the first carrier transport layer103 and the second carrier transport layer 104. Therefore, virtually nore-growth-associated impurities are observed at the heterojunctioninterface 110 between the second carrier transport layer 104 and thecarrier supply layer 105. Since the carrier supply layer 105 iscontinuously grown on the second carrier transport layer 104 afterre-growth of the second carrier transport layer 104, flatness of theheterojunction interface 110 between the second carrier transport layer104 and the carrier supply layer 105 is higher than that of theheterojunction interface between the first carrier transport layer 103and the carrier supply layer 105 in the case where the carrier supplylayer 105 is grown directly on the first carrier transport layer 103.Therefore, there is not reduced the mobility of 2DEG generated in thevicinity of the heterojunction interface 110 between the second carriertransport layer 104 and the carrier supply layer 105 and on the side ofthe second carrier transport layer 104. Thus, the HEMT 100 according toEmbodiment 1 exhibits a normally-off characteristic and low on-stateresistance.

From the viewpoints of sufficient reduction in amount ofre-growth-associated impurities at the heterojunction interface betweenthe second carrier transport layer 104 and the carrier supply layer 105,as well as improvement of flatness of the interface, the thickness ofthe second carrier transport layer 104 is preferably 50 nm or more.

In the HEMT 100, the thickness of the insulating film 108 is adjusted tobe smaller than that of the second carrier transport layer 104 so thatthe level of the top surface 108a of the insulating film 108 formed onthe first carrier transport layer 103 is below that of theheterojunction interface 110 between the second carrier transport layer104 and the carrier supply layer 105; i.e., the top surface 108a isnearer to the first carrier transport layer 103 than the heterojunctioninterface 110 is. With this structure, when positive voltage is appliedto the gate electrode 109, a larger amount of electrons can beaccumulated in the vicinity of the two lateral end surfaces 111. As aresult, on-state resistance can be further reduced.

Next will be described a method for producing the HEMT 100 withreference to FIG. 2.

Firstly, an AlN buffer layer 102 is formed on an Si substrate 101through MOCVD in a MOCVD growth chamber. Then, a first carrier transportlayer 103 is formed from undoped GaN on the buffer layer 102 throughMOCVD (FIG. 2A). Hydrogen and nitrogen are employed as carrier gases;ammonia is employed as a nitrogen source; TMG (trimethylgallium) isemployed as a Ga source; and TMA (trimethylaluminum) is employed as anAl source.

Subsequently, after the Si substrate 101 having layers 102 and 103 istaken out of the MOCVD growth chamber, an SiO₂ mask 113 is formed on aspecific region of the first carrier transport layer 103 through CVD ina plasma CVD chamber, and the mask 113 is not formed on two regionsseparated by the mask 113, to thereby expose the surface of the firstcarrier transport layer 103 (FIG. 2B). No particular limitation isimposed on the material of the mask 113, so long as the materialinhibits growth of a Group III nitride semiconductor. The mask 113 maybe formed of, in place of SiO₂ film, an insulating film of, for example,Si₃N₄, Al₂O₃, HfO₂, or ZrO₂.

Subsequently, the Si substrate 101 having layers 102, 103 and the mask113 is returned into the MOCVD growth chamber. The surface of the firstcarrier transport layer 103 is contaminated with impurities at thestages of mask formation process and transport processes of thesubstrate between the MOCVD growth chamber and the plasma processchamber. A second carrier transport layer 104 made of undoped GaN isre-grown on the first carrier transport layer 103 through MOCVD in theMOCVD growth chamber. Since GaN is not grown on the mask 113 because ofinhibition of crystal growth, the second carrier transport layer 104 isselectively re-grown only on the two regions separated by the mask 113(FIG. 2C). Since the growth of the first carrier transport layer 103 andthe second carrier transport layer 104 is not continuous but the secondcarrier transport layer 104 is re-grown after forming the mask 113 inthe chamber other than the MOCVD growth chamber as described above,flatness of the interface between the first carrier transport layer 103and the second carrier transport layer 104 is degraded, and impuritiesare incorporated at the interface. However, as growth of the secondcarrier transport layer 104 proceeds, flatness of the growing surface ofthe layer 104 is improved, and density of growth-associated impuritieson the growing surface is decreased.

After the second carrier transport layer 104 has been grown so as tohave a specific thickness, an Al_(0.25)Ga_(0.75)N carrier supply layer105 is successively grown thereon through MOCVD. During this growthprocess, crystal growth on the mask 113 is also inhibited. Therefore,the carrier supply layer 105 is grown only on the two second carriertransport layers 104. When the growth of the carrier supply layer 105 isstarted, flatness of the surface of the second carrier transport layer104, on which the carrier supply layer 105 is grown, has been alreadyimproved, and density of impurities on the surface has been decreasedsubstantially to zero. Therefore, flatness of the heterojunctioninterface between the second carrier transport layer 104 and the carriersupply layer 105 is high, and virtually no growth-associated impuritiesare observed in the vicinity of the interface. After the carrier supplylayer 105 has been grown so as to have a specific thickness, the mask113 is removed (FIG. 2D).

Subsequently, an SiO₂ insulating film 108 is formed on a region of thefirst carrier transport layer 103 on which the second carrier transportlayers 104 are not provided; on two mutually facing lateral end surfaces111 of two separate laminate structures each including the secondcarrier transport layer 104 and the carrier supply layer 105; and on thecarrier supply layers 105. The insulating film 108 serves as both a gateinsulating film and a protective film of the carrier supply layer 105for common use to reduce the number of production processes thereby. Theinsulating film 108 is formed through, for example, CVD, sputtering, orALD. Subsequently, the insulating film 108 is removed so as to exposeregions of the carrier supply layer 105 on which a source electrode 106and a drain electrode 107 are formed, and the source electrode 106 andthe drain electrode 107 are formed on the thus-exposed regions of thecarrier supply layer 105 through vapor deposition and the lift-offprocess. A gate electrode 109 is formed on a portion of the insulatingfilm 108, through vapor deposition and the lift-off process, the portionincluding an area above a region of the first carrier transport layer103 on which the second carrier transport layer 104 is not provided; twofront areas of the two lateral end surfaces 111; and an area above thecarrier supply layer 105 in the vicinity of the lateral end surfaces111. Thus, the HEMT 100 shown in FIG. 1 is produced.

In the HEMT 100 produced through this production method, flatness of theheterojunction interface between the second carrier transport layer 104and the carrier supply layer 105 is improved, and virtually nogrowth-associated impurities are observed in the vicinity of theinterface. Therefore, the HEMT 100 exhibits a normally-offcharacteristic, and low on-state resistance.

In the aforementioned production method for the HEMT 100, the mask 113employed for crystal growth is removed after formation of the carriersupply layer 105. However, the mask 113 may be left and employed as agate insulating film.

Embodiment 2

FIG. 3 shows the configuration of an HEMT 200 according to Embodiment 2.The HEMT 200 has the same configuration as the HEMT 100 according toEmbodiment 1, except that the second carrier transport layer 104, thecarrier supply layer 105, the insulating film 108, and the gateelectrode 109 are respectively replaced with a second carrier transportlayer 204, a carrier supply layer 205, an insulating film 208, and agate electrode 209. The second carrier transport layer 204 and thecarrier supply layer 205 differ from the second carrier transport layer104 and the carrier supply layer 105 only in that two mutually facinglateral end surfaces 220 of two separate laminate structures eachincluding the second carrier transport layer 204 and the carrier supplylayer 205 are inclined. Similar to the case of the second carriertransport layer 104 and the carrier supply layer 105, the second carriertransport layer 204 and the carrier supply layer 205 are formed throughselective re-growth and selective growth, respectively. The lateral endsurfaces 220 are inclined such that the area of a horizontal crosssection of the second carrier transport layer 204 and the carrier supplylayer 205 parallel to the main surface of the device (i.e., parallel tothe main surface of the substrate 101) is reduced with increasingdistance between the cross section and the first carrier transport layer103. The insulating film 208 and the gate electrode 209 are the same asthe insulating film 108 and the gate electrode 109, respectively, exceptthat the insulating film 208 and the gate electrode 209 are formed onthe inclined lateral end surfaces 220.

The inclined lateral end surfaces 220 can be formed by growing thesecond carrier transport layer 204 and the carrier supply layer 205under specific growth conditions. Under such specific growth conditions,the second carrier transport layer 204 and the carrier supply layer 205can be grown in a direction perpendicular to the main surface of thedevice (i.e., c-plane of Group III nitride semiconductor) with keepingfacet surfaces (e.g., (10-11) plane) inclined with respect to c-plane ata side wall. The thus-inclined facet surfaces serve as the lateral endsurfaces 220.

Thus, when the lateral end surfaces 220 of the second carrier transportlayer 204 and the carrier supply layer 205 are inclined, electric fieldcrowding is relaxed in the vicinity of the surface of the first carriertransport layer 103 which is in contact with the gate electrode 209 viathe insulating film 208, and in the vicinity of the lateral end surfaces220. Therefore, the HEMT 200 exhibits breakdown voltage higher than thatof the HEMT 100.

Embodiment 3

FIG. 4 shows the configuration of an HEMT 300 according to Embodiment 3.The HEMT 300 has the same configuration as the HEMT 100 according toEmbodiment 1, except that the carrier supply layer 105 is replaced witha carrier supply layer 305 as described below. The carrier supply layer305 has a three-layer structure including a first carrier supply layer305 a formed of undoped GaN, a second carrier supply layer 305 b formedof undoped AlGaN, and a third carrier supply layer 305 c formed ofundoped AlN, which layers are sequentially stacked on the second carriertransport layer 104. The second carrier transport layer 104 isselectively re-grown on the first carrier transport layer 103 and thecarrier supply layer 305 is selectively grown on the second carriertransport layer 104 similar to the case of the second carrier transportlayer 104 and the carrier supply layer 105 in Embodiment 1,respectively.

In the HEMT 300, the second carrier transport layer 104 and the carriersupply layer 305 having a three-layer structure are formed on the firstcarrier transport layer 103 through selective re-growth and selectivegrowth, respectively in a manner similar to that described above.Therefore, in the HEMT 300, reduction in mobility of 2DEG is suppressed,and on-state resistance is reduced.

The carrier supply layer 305 may have another multi-layer structure. Forexample, the carrier supply layer 305 may have a laminate structureincluding two layers, three layers, or four or more layers, such asGaN/AlGaN (which refers to a laminate structure in which GaN and AlGaNare sequentially provided on the first carrier transport layer 103, thesame shall apply hereinafter in this paragraph), InGaN/AlGaN,InGaN/AlGaN/AlN or InGaN/GaN/AlGaN/AlN. Alternatively, the carriersupply layer 305 may have a structure including a plurality of layersdoped with n-type impurities at different concentrations, such asn⁻-AlGaN/n-AlGaN.

Embodiment 4

FIG. 5 shows the configuration of an HEMT 400 according to Embodiment 4.The HEMT 400 has the same configuration as the HEMT 100 according toEmbodiment 1, except that the second carrier transport layer 104 and thecarrier supply layer 105 are replaced with three layer pairs eachincluding a second carrier transport layer 404 and a carrier supplylayer 405; specifically, a second carrier transport layer 404 a, acarrier supply layer 405 a, a second carrier transport layer 404 b, acarrier supply layer 405 b, a second carrier transport layer 404 c, anda carrier supply layer 405 c are sequentially stacked on the firstcarrier transport layer 103. Similar to the case of the second carriertransport layer 104 and the carrier supply layer 105 of the HEMT 100,the three layer pairs of the second carrier transport layer 404 and thecarrier supply layer 405 are formed on the first carrier transport layer103 through selective re-growth and selective growth.

2DEG layers are formed respectively at the heterojunction interface 440a between the second carrier transport layer 404 a and the carriersupply layer 405 a and on the side of the second carrier transport layer404 a; at the heterojunction interface 440 b between the second carriertransport layer 404 b and the carrier supply layer 405 b and on the sideof the second carrier transport layer 404 b; and at the heterojunctioninterface 440 c between the second carrier transport layer 404 c and thecarrier supply layer 405 c and on the side of the second carriertransport layer 404 c. Since the second carrier transport layer 404 a isformed on the first carrier transport layer 103 through selectivere-growth and the other second carrier transport layers 404 b, 404 c andthe carrier supply layers 405 a, 405 b and 405 c are formed on thesecond carrier transport layers 404 a, 404 b and 404 c, respectivelythrough selective growth, the heterojunction interfaces 440 a, 440 b,and 440 c exhibit high flatness, and virtually no growth-associatedimpurities are incorporated at regions in the vicinity of theheterojunction interfaces 440 a, 440 b, and 440 c. Therefore, reductionin mobility of 2DEG generated in the vicinity of the heterojunctioninterfaces 440 a, 440 b, and 440 c is suppressed, and on-stateresistance is reduced.

As described above, the HEMT 400 according to Embodiment 4 has astructure including three 2DEG layers, in which reduction in mobility of2DEG is suppressed. Therefore, the HEMT 400 exhibits further reducedon-state resistance.

In Embodiment 4, the second carrier transport layers 404 a, 404 b, and404 c have the same composition, and the carrier supply layers 405 a,405 b, and 405 c have the same composition. However, the second carriertransport layers 404 a, 404 b, and 404 c may have differentcompositions, and the carrier supply layers 405 a, 405 b, and 405 c mayhave different compositions, so long as heterojunction interfaces areformed between the second carrier transport layer 404 a and the carriersupply layer 405 a, between the second carrier transport layer 404 b andthe carrier supply layer 405 b, and between the second carrier transportlayer 404 c and the carrier supply layer 405 c, and a 2DEG layer isformed in the vicinity of each of the heterojunction interfaces.

Embodiment 5

FIG. 6 shows the configuration of an HEMT 500 according to Embodiment 5.The HEMT 500 has the same configuration as the HEMT 100 according toEmbodiment 1, except for the below-described modification. In the HEMT500, a ZrO₂ insulating film 550 having a specific dielectric constanthigher than that of the SiO₂ insulating film 108 is formed on a regionof the insulating film 108 on which neither the source electrode 106 northe drain electrode 107 is formed, which region is located above thecarrier supply layer 105. A gate electrode 509 is formed, via theinsulating film 108, on a region of the first carrier transport layer103 on which the second carrier transport layers 104 are not provided,and on two mutually facing lateral end surfaces 511 of the two separatelaminate structures each including the second carrier transport layer104 and the carrier supply layer 105. Also, the gate electrode 509extends 0.5 μm from the lateral end surface 511 (on the side of thesource electrode 106) toward the source electrode 106 such that the gateelectrode 509 is provided on the insulating film 550, and the gateelectrode 509 extends 1.5 μm from the lateral end surface 511 (on theside of the drain electrode 107) toward the drain electrode 107 suchthat the gate electrode 509 is provided on the insulating film 550.

In the structure of the HEMT 500, the insulating film 550, which has aspecific dielectric constant higher than that of the insulating film108, is provided between the insulating film 108 and the gate electrode509 extending from the lateral end surface 511 (on the side of the drainelectrode 107) of the second carrier transport layer 104 and the carriersupply layer 105 toward the drain electrode 107. Therefore, upon OFFoperation, electric field intensity is reduced in the insulating film108 on the carrier supply layer 105 in the vicinity of the lateral endsurface 511 on the side of the drain electrode 107. Thus, the HEMT 500exhibits further improved breakdown voltage.

Embodiment 6

FIG. 7 shows the configuration of an HEMT 600 according to Embodiment 6.The HEMT 600 has the same configuration as the HEMT 100 according toEmbodiment 1, except for the below-described modification. In the HEMT600, an SiN insulating film 650 is formed on a region of the carriersupply layer 105 on which neither the source electrode 106 nor the drainelectrode 107 is formed. An SiO₂ insulating film 608 is formedcontinuously on the first carrier transport layer 103, on two mutuallyfacing lateral end surfaces 611 of the two separate laminate structureseach including the second carrier transport layer 104 and the carriersupply layer 105, and on the insulating film 650. A gate electrode 609is formed, via the insulating film 608, on the first carrier transportlayer 103 and on the lateral end surfaces 611. Also, the gate electrode609 is formed on the insulating film 608 so as to extend 0.5 μm from thelateral end surface 611 (on the side of the source electrode 106) towardthe source electrode 106, and the gate electrode 609 is formed on theinsulating film 608 so as to extend 1.5 μm from the lateral end surface611 (on the side of the drain electrode 107) toward the drain electrode107.

In the HEMT 600, the SiO₂ insulating film 608 exhibiting high breakdownvoltage is provided on the lateral end surfaces 611 and on a region ofthe first carrier transport layer 103 in which the second carriertransport layers 104 are not formed, in which electric field intensityincreases upon ON operation. Also, the SiO₂ insulating film 608exhibiting high breakdown voltage is provided directly below the end (onthe side of the drain electrode) of the gate electrode 609 at whichelectric field intensity increases upon OFF operation. The insulatingfilm 650 is provided on a region of the carrier supply layer 105 whichis directly below the end (on the side of the drain electrode) of thegate electrode 609 at which electric field intensity increases upon OFFoperation. Since the insulating film 650 is formed of SiN, interfacestate density can be reduced at the interface between the carrier supplylayer 105 and the insulating film 650, and characteristic deterioration(e.g., current collapse (i.e., considerable reduction in drain currentupon high-voltage operation)) can be suppressed, as compared with thecase where the insulating film 650 is formed of SiO₂.

Thus, the HEMT 600 has a structure in which the insulating film providedon a region requiring high breakdown voltage is formed of a materialdifferent from that of the insulating film provided on a regionrequiring reduction in interface state density. Therefore, the HEMT 600realizes improvement of breakdown voltage, as well as prevention ofcharacteristic deterioration due to high interface state density.

Embodiment 7

FIG. 8 shows the configuration of an HEMT 700 according to Embodiment 7.The HEMT 700 has the same configuration as the HEMT 100 according toEmbodiment 1, except that a carrier transport preventing layer 750 isprovided between the buffer layer 102 and the first carrier transportlayer 103. The carrier transport preventing layer 750 is formed of ap-GaN layer doped with Mg (1×10¹⁹ cm⁻³) and having a thickness of 100 nmand hole concentration of 1×10¹⁷ cm⁻³.

The carrier transport preventing layer 750 exhibits high resistance toelectron flow. Therefore, when high bias voltage is applied between thesource electrode and the drain electrode upon OFF operation, the carriertransport preventing layer 750 can block a current path via a regionaway from the heterojunction interface between the second carriertransport layer 104 and the carrier supply layer 105. Thus, in the HEMT700, leakage current between the source electrode and the drainelectrode is reduced upon OFF operation. Similar to the case of the HEMT100, the HEMT 700 exhibits a normally-off characteristic and reducedon-state resistance.

When the carrier transport preventing layer 750 is provided, thedistance between the carrier transport preventing layer 750 and thecarrier supply layer 105 must be adjusted to a specific distance ormore. Specifically, the total thickness of the first carrier transportlayer 103, the second carrier transport layer 104, and the carriersupply layer 105 is preferably adjusted to 100 nm or more. This isbecause, when the distance between the carrier transport preventinglayer 750 and the carrier supply layer 105 is small, upon formation ofthe first carrier transport layer 103, the second carrier transportlayer 104, and the carrier supply layer 105, Mg incorporated into thecarrier transport preventing layer 750 may be diffused into the carriersupply layer 105, resulting in reduction in concentration or mobility of2DEG. Also, the carrier transport preventing layer 750, which is of ap-type, may effect reduction in 2DEG concentration.

In Embodiment 7, the carrier transport preventing layer 750 is formed ofp-GaN. However, no particular limitation is imposed on the material ofthe carrier transport preventing layer 750, so long as the material canprevent transport of electrons in a region away from the second carriertransport layer 104. For example, the carrier transport preventing layer750 may have a conduction type different from that of the first carriertransport layer 103. Since the first carrier transport layer 103 isformed of undoped GaN (i.e., low-concentration n-type layer), thecarrier transport preventing layer 750 may be formed of p-GaN or i-GaN.

The carrier transport preventing layer 750 may be formed of AlGaN, whichhas a bandgap larger than that of undoped GaN (i.e., the material of thefirst carrier transport layer 103). When the carrier transportpreventing layer 750 is formed of AlGaN, negative polarized charges aregenerated at the heterojunction interface between the first carriertransport layer 103 and the carrier transport preventing layer 750, andthese charges and discontinuity of bands at the heterojunction interfaceact as barriers for electrons. Thus, when high bias voltage is appliedbetween the source electrode and the drain electrode upon OFF operation,the carrier transport preventing layer 750 can block a current path viaa region away from the heterojunction interface between the secondcarrier transport layer 104 and the carrier supply layer 105, and canreduce leakage current between the source electrode and the drainelectrode. When the thickness of the carrier transport preventing layer750 is excessively small, electrons penetrate the carrier transportpreventing layer 750 by means of the tunnel effect, and leakage currentflows through the buffer layer 102. Therefore, the carrier transportpreventing layer 750 preferably has a thickness of 100 nm or more.

The carrier transport preventing layer 750 may be formed of InGaN, whichhas a bandgap smaller than that of the material of the buffer layer 102.When the carrier transport preventing layer 750 is formed of InGaN,negative polarized charges are generated at the heterojunction interfacebetween the buffer layer 102 and the carrier transport preventing layer750, and these charges and discontinuity of bands at the heterojunctioninterface act as barriers for electrons. Thus, when high bias voltage isapplied between the source electrode and the drain electrode upon OFFoperation, the carrier transport preventing layer 750 can block acurrent path via a region away from the heterojunction interface betweenthe second carrier transport layer 104 and the carrier supply layer 105,and can reduce leakage current between the source electrode and thedrain electrode. Since the material of the carrier transport preventinglayer 750 has a bandgap smaller than that of undoped GaN (i.e., thematerial of the first carrier transport layer 103), leakage currentflows through the carrier transport preventing layer 750. Therefore,preferably, the amount of leakage current which flows through thecarrier transport preventing layer 750 is reduced by adjusting thethickness of the carrier transport preventing layer 750 to 200 nm orless. More preferably, the carrier transport preventing layer 750 isformed of p-InGaN or i-InGaN.

Embodiment 8

FIG. 9 shows the configuration of a diode 800 according to Embodiment 8.In the diode 800, the source electrode 106 and the drain electrode 107of the HEMT 100 according to Embodiment 1 are replaced with an anode 806and a cathode 807, respectively, and the gate electrode 109 of the HEMT100 is replaced with a gate electrode 809. The gate electrode 809 isformed by extending the gate electrode 109 of the HEMT 100 toward theanode 806 so as to cover the anode 806. The anode 806 and the cathode807 have the same configuration as the source electrode 106 and thedrain electrode 107 of the HEMT 100 according to Embodiment 1; i.e., theanode 806 and the cathode 807 are formed of Ti/Al. The gate electrode809 is formed of Ni/Au.

Each of the anode 806 and the cathode 807 is in ohmic contact with thesecond carrier transport layer 104 via the carrier supply layer 105 bymeans of the tunnel effect. Under application of bias voltage, the gateelectrode 809 acts as a control electrode for controlling the amount ofelectrons in the vicinity of the surface of the first carrier transportlayer 103 which is in contact with the gate electrode 809 via theinsulating film 108, and in the vicinity of the two mutually facinglateral end surfaces 111 of the two separate laminate structures eachincluding the second carrier transport layer 104 and the carrier supplylayer 105.

Similar to the case of the HEMT 100 according to Embodiment 1, in thediode 800, a 2DEG layer is formed in the vicinity of the heterojunctioninterface 110 between the second carrier transport layer 104 and thecarrier supply layer 105 and on the side of the second carrier transportlayer 104. The second carrier transport layers 104 and the carriersupply layers 105 are provided in two regions separated by the gateelectrode 809. Therefore, the 2DEG layer is formed in separate tworegions; i.e., a region between the anode and the gate electrode, and aregion between the gate electrode and the cathode.

Operation of the diode 800 will now be described. When forward biasvoltage is applied between the anode 806 and the cathode 807 of thediode 800, electrons are accumulated in the vicinity of the surface ofthe first carrier transport layer 103 which is in contact, via theinsulating film 108, with the gate electrode 809 electrically connectedto the anode 806, and in the vicinity of the lateral end surfaces 111.By means of the thus-accumulated electrons, the 2DEG layer providedbetween the anode and the gate electrode is electrically connected tothe 2DEG layer provided between the gate electrode and the cathode, andcurrent flows between the anode 806 and the cathode 807. In contrast,when reverse bias voltage is applied between the anode 806 and thecathode 807, electrons are depleted in the vicinity of the gateelectrode 809 electrically connected to the anode 806, and 2DEG betweenthe gate electrode and the cathode is also depleted, resulting ininterruption of current flow.

Thus, in the diode 800 according to Embodiment 8, the amount ofelectrons are controlled by the gate electrode 809 via the insulatingfilm, whereby rectification is achieved.

Similar to the case of the HEMT 100 according to Embodiment 1 describedabove, in the diode 800 according to Embodiment 8, flatness of theheterojunction interface 110 between the second carrier transport layer104 and the carrier supply layer 105 is high, and virtually nogrowth-associated impurities are incorporated in the vicinity of theheterojunction interface 110, whereby the mobility of 2DEG is increased.Since the anode 806 is in ohmic contact with the second carriertransport layer 104, the rise voltage upon application of forward biasvoltage is nearly equal to zero. Thus, the diode 800 exhibits lowon-state resistance and on-state voltage.

In the diode 800, the gate electrode 809 is electrically connected tothe anode 806. Therefore, when reverse bias voltage is applied to thediode 800, the electric field intensity becomes highest at the end (onthe side of the cathode 807) of the gate electrode 809. The insulatingfilm 108 is formed at the cathode-side end of the gate electrode 809,and the gate electrode 809 is in contact, via the insulating film 108,with the second carrier transport layer 104 and the carrier supply layer105. Therefore, reverse leakage current can be considerably reduced atthe end of the gate electrode 809 with high electric field intensity.Thus, the diode 800 exhibits high breakdown voltage upon OFF operation.

The diode 800 according to Embodiment 8 has a structure in which thesource electrode 106 of the HEMT 100 according to Embodiment 1 isemployed as the anode 806, and the gate electrode 109 is connected tothe anode 806 by extending the gate electrode 109 toward the anode 806.The diode 800 may have another structure, so long as the sourceelectrode 106 of the HEMT 100 according Embodiment 1 is employed as theanode 806, and the anode 806 is electrically connected to the gateelectrode 109. For example, the diode 800 may have a structure in whichthe anode is electrically connected to the gate electrode 109 byextending the anode toward the gate electrode 109. Alternatively, thediode 800 may have a structure in which the anode and the gate electrode109 are indirectly connected by means of, for example, a wire electrode.Alternatively, the diode 800 may have a composite anode structure inwhich the anode and the gate electrode 109 are formed from the same(common) material.

The diode 800 according to Embodiment 8 has a structure in which thesource electrode 106 of the HEMT 100 according to Embodiment 1 isemployed as the anode, and the anode is electrically connected to thegate electrode. A diode exhibiting effects similar to those of the diode800 can be realized by providing a structure in which the drainelectrode of each of the HEMTs 200 to 700 according to Embodiments 2 to7 is employed as the anode, and the anode is electrically connected tothe gate electrode.

Embodiment 9

FIG. 10 shows the configuration of a power factor improving circuit 900according to Embodiment 9. The power factor improving circuit 900includes an AC power supply V, and a diode bridge 10 having four diodesD1 for rectifying AC voltage from the AC power supply V. Also, the powerfactor improving circuit 900 includes an HEMT 20 whose drain electrodeis connected to the positive (higher voltage) output terminal (on the DCside) of the diode bridge 10 via an inductor L, and whose sourceelectrode is connected to the negative (lower voltage) output terminal(on the DC side) of the diode bridge 10; and a control circuit 30 whichis connected to the gate electrode of the HEMT 20. A circuit connectinga diode D2 and a capacitor C in series is connected between the sourceelectrode and the drain electrode of the HEMT 20, and the capacitor C isconnected to a resistor R in parallel. The power factor improvingcircuit 900 improves the power factor of the AC power supply V bycontrolling ON/OFF of the HEMT 20 by means of the control circuit 30 onthe basis of, for example, output voltage or current which flows throughthe diode bridge 10.

The power factor improving circuit 900 having the aforementionedconfiguration employs, as the diode D1 or D2, the diode 800 according toEmbodiment 8, and, as the HEMT 20, the HEMT 100 according toEmbodiment 1. Therefore, the power factor improving circuit 900 exhibitsreduced loss, and realizes highly effective operation with low loss.

In the aforementioned Embodiments, the semiconductor device of thepresent invention is applied to an HEMT or a diode. However, the presentinvention is also applicable to another semiconductor device in which a2DEG layer formed at the interface between a carrier transport layer anda carrier supply layer serves as a channel; for example, aheterojunction bipolar transistor (HET).

The HEMTs according to Embodiments 1 to 7 may incorporate a field platestructure for further improving breakdown voltage.

The semiconductor device of the present invention exhibits low on-stateresistance. Therefore, when the semiconductor device of the presentinvention is applied to a power converter, the power converter realizeshigh performance.

What is claimed is:
 1. A method for producing a semiconductor device,comprising: forming a first carrier transport layer comprising a GroupIII nitride semiconductor; forming a mask on a region of the firstcarrier transport layer; selectively re-growing a second carriertransport layer on an unmasked region of the first carrier transportlayer, the second carrier transport layer comprising a Group III nitridesemiconductor; and selectively growing a carrier supply layer on thesecond carrier transport layer, the carrier supply layer comprising aGroup III nitride semiconductor having a bandgap different from that ofthe Group III nitride semiconductor of the second carrier transportlayer.
 2. A method for producing a semiconductor device according toclaim 1, wherein laminate structures comprising the second carriertransport layer and the carrier supply layer are formed on two separateregions of a surface of the first carrier transport layer, the twoseparate regions being separated by the mask; and the method furthercomprising; removing the mask; forming an insulating film on a region ofthe first carrier transport layer sandwiched between the two separateregions and also on the mutually facing lateral end surfaces of the twoseparate laminate structures; and forming a control electrode on theinsulating film.
 3. A method for producing a semiconductor deviceaccording to claim 2, wherein the insulating film is also formed on topsurfaces of the two separate regions of the carrier supply layer, andthe control electrode is formed to extend, via the insulating film, ontothe carrier supply layers.
 4. A method for producing a semiconductordevice according to claim 2, further comprising: forming a firstelectrode on the carrier supply layer of one of the two separate regionsto be electrically connected to the second carrier transport layer ofthe same region; forming a second electrode on the carrier supply layerof the other region to be electrically connected to the second carriertransport layer of the same region.
 5. A method for producing asemiconductor device according to claim 3, wherein a portion or anentirety of the insulating film is formed of a plurality of layers.
 6. Amethod for producing a semiconductor device according to claim 3,wherein the insulating film is formed such that a portion of theinsulating film provided on the first carrier transport layer exhibits aproperty different from that of a portion of the insulating filmprovided on the carrier supply layer.
 7. A method for producing asemiconductor device according to claim 2, wherein the insulating filmis formed to have a thickness smaller than that of the second carriertransport layer.
 8. A method for producing a semiconductor deviceaccording to claim 2, wherein the carrier supply layer is formed to havea plurality of layers.
 9. A method for producing a semiconductor deviceaccording to claim 2, further comprising: selectively growing one ormore layer pairs on the two separate regions of the surface of the firstcarrier transport layer, wherein each pair is formed to comprise anunder layer comprising a Group III nitride semiconductor and an upperlayer comprising a Group III nitride semiconductor having a bandgaplarger than that of the Group III nitride semiconductor of the underlayer, wherein an under layer which contacts with the carrier supplylayer has a bandgap smaller than that of the Group III nitridesemiconductor of the carrier supply layer.
 10. A method for producing asemiconductor device according to claim 2, wherein the second carriertransport layer is formed such that a level of an interface between thecarrier supply layer and the second carrier transport layer is higherthan a level of a top surface of the insulating film on an areasandwiched between the two separate regions.